Ppg Period Setting Buffer Register (Pcsr0 To Pcsr2) - Fujitsu MB90460 Series Hardware Manual

F2mc-16lx 16-bit microcontroller
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13.4.2

PPG Period Setting Buffer Register (PCSR0 to PCSR2)

PPG period setting buffer register is used to set the period of the output pulses
generated by PPG.
■ PPG Period Setting Buffer Register (PCSR0 to PCSR2)
Figure 13.4-3 PPG Period Setting Buffer Register (PCSR0 to PCSR2)
PPG Period Setting Buffer Register (Upper)
Address: ch.0 00003B
ch.1 000043
ch.3 00004B
Read/write
Initial value
PPG Period Setting Buffer Register (Lower)
Address: ch.0 00003A
ch.1 000042
ch.3 00004A
These are 16-bit registers that are used to set the period of the output pulses generated by PPG. The initial
value of them are undetermined, so that these registers must be written before starting an operation. Word
access to these registers are recommended. These registers are write-only.
Data transfer from period setting buffer register to period setting register will be at counter borrow or
trigger or retrigger if enabled.
Note:
In case of updating period setting buffer register, duty setting buffer register must be written after
writing to period setting buffer register. Only updating period setting buffer register is prohibited.
bit
15
H
H
CS15
CS14
H
W
W
X
X
7
bit
H
H
CS07
CS06
H
Read/write
W
W
Initial value
X
X
14
13
12
11
CS13 CS12
CS11
CS10
W
W
W
X
X
X
6
5
4
CS05 CS04
CS03
W
W
W
X
X
X
CHAPTER 13 16-BIT PPG TIMER
10
9
8
CS09
CS08
W
W
W
X
X
X
3
2
1
0
CS02
CS01
CS00
W
W
W
X
X
X
PCSR0 to
PCSR2
PCSR0 to
PCSR2
265

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