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■ PWC control Status Register, Lower Byte (PWCSL0/PWCSL1)
Figure 16.4-3 PWC Control Status Register (PWCSL0/PWCSL1)
Address
bit
7
CKS1 CKS0
ch.0: 000008
H
ch.1: 000028
H
R/W
X
: Indeterminate
R/W : Read and write
: Initial value
—
: Not used
6
5
4
Reserved Reserved
R/W
R/W
R/W
MOD2 MOD1 MOD0 Operation mode / count edge selection
S/C
CKS1 CKS0
3
2
1
0
MOD2 MOD1 MOD0 00000000
S/C
R/W
R/W
R/W
R/W
0
0
0
Timer mode and no pulse output
Timer mode and pulse output (PWO pin valid):
0
0
1
reload mode only
All edge-to-edge pulse-width measurement
0
1
0
mode (rising edge or falling edge to falling edge
or rising edge)
Division period measurement mode
0
1
1
(when the input divider is used)
Rising edge-to-rising edge period measurement
1
0
0
mode (rising edge to rising edge)
H pulse-width measurement mode
1
0
1
(rising edge to falling edge)
L pulse-width measurement mode
1
1
0
(falling edge to rising edge)
Falling edge-to-falling edge period measurement
1
1
1
mode (falling edge to falling edge)
Count mode
selection
Single
No reload (one shot) Stop after one
0
measurement mode
Reload
Continuous
(reload timer)
1
measurement mode
Buffer register is
valid
Machine clock divided by 4
0
0
µ
(0.25
s for machine cycle at 16 MHz)
Machine clock divided by 16
0
1
µ
(1.0
s for machine cycle at 16 MHz)
Machine clock divided by 32
1
0
µ
(2.0
s for machine cycle at 16 MHz)
1
1
Setting prohibited (undefined)
CHAPTER 16 PWC Timer
Initial value
B
Pulse-width count
Timer mode
mode
measurement
Continuous
measurement:
Buffer register is
valid
Count clock selection
441
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