Delayed Interrupt Generator Module Register - Fujitsu MB90460 Series Hardware Manual

19.2

Delayed Interrupt Generator Module Register

This section lists the delayed interrupt generator module register.
■ Delayed Interrupt Generator Module Register (DIRR)
Figure 19.2-1 Delayed Interrupt Generator Module Register (DIRR)
Address bit 15
—
00009F
H
—
R/W: Read and write
: Initial value
— : Not used
Table 19.2-1 Delayed Interrupt Generator Module Register (DIRR)
Bit name
bit15
to Reserved bits
bit9
R0:
bit8 Delayed interrupt
request bit
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE
14 13 12 11
—
—
— —
— — — —
• Both "0" and "1" may be written to the reserved bit area, however, the set bit and clear
bit instructions should be used to access this register to prepare for future expansion.
• This bit is used to controls the generation or clearing of a delayed interrupt request.
• Writing "1" to this register generates a delayed interrupt request.
• Writing "0" to this register clears the delayed interrupt request.
• The register is cleared at reset.
• Both "0" and "1" may be written to the reserved bit area. However, the set bit and clear
bit instructions should be used to access this register to prepare for future expansion.
10 9 8 Initial value
— — R0 -------0
— — R/W
R0 Delayed interrupt request
0 Clears delayed interrupt request
1 Generates delayed interrupt request
Function
B
537