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CHAPTER 16 PWC Timer
Table 16.4-1 PWC Control Status Register (PWCSH0/PWCSH1)
Bit name
bit15,
STRT, STOP:
bit14
Start and Stop bits
EDIR:
bit13
End interrupt
request flag bit
EDIE:
bit12
End interrupt
enable bit
OVIR:
bit11
Overflow interrupt
request bit
OVIE:
bit10
Overflow interrupt
request enable bit
ERR:
bit9
Error flag bit
POUT:
bit8
Pulse output bit
440
•
These bits are used to start, restart, and stop the 16-bit up-count timer.
•
When these bits are read, the timer operation status is returned.
•
These bits can be read and written. The meaning of bits depend on whether they are read or written.
•
In read-modify-write operation, "11
•
When the STRT and STOP bits are written to start and stop the timer, a bit manipulation instruction
(such as bit clear instruction) can be used. However, when the operation status (which always indicates
that the timer is operating, for example) is read, a bit manipulation instruction cannot be used.
•
This bit indicates that measurement terminated in pulse-width measurement mode.
•
When pulse-width measurement terminates, the bit is set (PWC0/PWC1 contains the measurement
result).
•
This bit is cleared automatically when the measurement result in PWC data buffer register, PWC0/
PWC1, is read.
•
In timer mode, this bit is meaningless.
•
This bit is read-only, writing this bit is meaningless.
•
This bit is used to control a measurement termination interrupt request in pulse-width count mode.
•
When this bit is "1" and EDIR is set to "1", the end interrupt request will be generated to CPU.
•
Always set "0" in timer mode.
•
This bit is used to specify when the 16-bit up-count timer overflows. The operation affects all modes.
•
When timer overflow occurs (FFFF
•
Writing "0" will clear the bit.
•
Writing "1" has no effect.
•
In read-modify-write operation, "1" is always read.
(Note)
In H/L pulse-width count mode, do not use this bit for pulse-width time measurement.
•
This bit is used to enable timer overflow interrupt request.
•
When this bit is "1" and OVIR is set to "1", the overflow interrupt request will be generated to CPU.
(Note)
In the H/L pulse-width count mode, set this bit to "0".
•
This bit is used to execute a continuous count in the pulse-width count mode. This flag indicates that
the next count has been completed before the previous count result is read from PWC0/PWC1. If this
state occurs, PWC0/PWC1 is overwritten by new count result and the previous result is lost. The count
operation continues regardless of the value of this bit.
•
The bit is read-only. Writing to this bit is meaningless.
•
When the count result that has not been read is overwritten by the next result, the bit is set.
•
This bit is cleared automatically when the measurement result in PWC data buffer register, PWC0/
PWC1, is read.
•
When the 16-bit up-count timer overflows in timer mode, this bit is reversed.
•
In the pulse-width count mode, this bit is meaningless.
•
The bit can be read and written. However, the bit can be written only if the timer stops (both bit15:
STRT and bit14: STOP are set to "0"). If the bit is written during timer operation (both bit15: STRT and
bit14: STOP are set to "1"), the bit value remains unchanged.
•
When the POUT value is "0" and the timer overflows in the range from FFFF
stops and "1" is written, the bit is set.
•
When the POUT value is "1" and the timer overflows in the range from FFFF
stops and "0" is written, the bit is cleared. The bit is also cleared by reset.
Function
" is always read.
B
to 0000
), the bit is set.
H
H
to 0000
or the timer
H
H
to 0000
or the timer
H
H
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