Fujitsu MB90460 Series Hardware Manual page 510

[Dedicated baud rate generator]
CDCR0/CDCR1 : MD, DIV2 to DIV0
(Prescaler enable and selection bits)
φ
Machine clock prescaler
[Internal timer]
TMCSR0/TMCSR1 : CSL1, CSL0
2
Clock selector
1
φ/2
φ/2 3
φ
Prescaler
16-bit reload timer 0
[External clock]
P42/SCK0, P62/SCK1
Pin
φ : Machine clock frequency
Figure 17.6-1 Baud Rate Selection Circuit
SMR0/SMR1 : CS2 to CS0
(Clock selection bits)
4
Down
UF
counter
φ/2 5
SMR0/SMR1 : MD1
(Synchronous or asynchronous clock selection)
3
Clock selector
When the bits
are 000
Frequency divider
(synchronous)
Frequency divider
(asynchronous)
Selects the internal fixed
division ratios
When the bits
are 110
1/1 (synchronous)
1/16 (asynchronous)
When the bits
are 111
1/1 (synchronous)
1/16 (asynchronous)
CHAPTER 17 UART
to 101
B B
B
Baud rate
SCKI
B
491