Fujitsu MB90460 Series Hardware Manual page 173

CHAPTER 7 INTERRUPT
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
ER0
STACK
RW100
STACK_T
STAC
-------------------Main program------------------------------------------------------------------------------------------
CODE
START:
154
EQU 000102H
EQU 000103H
EQU 000104H
EQU 000105H
EQU 000106H
EQU 000107H
EQU EIRR:0
SSEG;Stack
RW1
KENDS
CSEG
AND CCR, #0BFH
MOV RP, #00
MOV A, #STACK_T
MOV SSB, A
MOVW A, #STACK_T
MOVW SP, A
MOV I:DDR1, #00000000B ; Sets the P10/INT0 pin to input
MOV BAPL, #00H
MOV BAPM, #30H
MOV BAPH, #00H
MOV ISCS, #00010001B
MOV IOAL, #00H
MOV IOAH, #00H
MOV DCTL, #64H
MOV DCTH, #00H
MOV I:ICR04, #00001000B ;EI
MOV I:ELVR, #00000001B ;Requests that INT0 be made H level
MOV I:EIRR, #00H
;Upper buffer address pointer
2
;EI OS status
;Lower I/O address pointer
;Upper I/O address pointer
;Low-order data counter
;High-order data counter
;Definition of external interrupt request flag bit
;Clears the I flag of the CCR in the PS and
prohibits interrupts
;Sets the register bank pointer
;Sets the system stack
;Sets the stack pointer, then
;Sets SSP because the S flag = 1
;Sets the buffer address (003000H)
;No I/O address update, byte transfer,
buffer address updated
I/O -> buffer transfer, terminated by the
peripheral function
;Sets the transfer source address
(port 0: 000000H)
;Sets the number of transfer bytes
(100 bytes)
2 2
OS channel 0, EI OS enable,
interrupt level 0 (highest priority)
;Clears the INT0 interrupt cause