CHAPTER 3 CPU
3.1
CPU
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The F
MC-16LX CPU is a 16-bit CPU designed for use in applications, such as welfare
and mobile equipment, which require high-speed real-time processing. The instruction
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set of the F
MC-16LX was designed for controllers so that it can perform various types
of control at high speed and efficiency.
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The F
MC-16LX CPU process not only 16-bit data but also 32-bit data using a built-in 32-
bit accumulator. Memory space, which can be extended up to 16M bytes, can be
accessed in either linear or bank access mode. The instruction set inherits the AT
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architecture of F
MC-8L, and has additional instructions supporting high-level
languages. In addition, it has an extended addressing mode, enhanced multiply/divide
instructions and reinforced bit manipulation instructions. The features of the F
16LX CPU are shown below:
■ CPU
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Minimum instruction execution time: 62.5 ns (when the source oscillation is 4 MHz and the PLL clock is
multiplied by 4)
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Maximum memory address space: 16M bytes. Access in linear or bank addressing mode
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Instruction set optimum for controller applications
Many data types (bit, byte, word and long word)
As many as 23 addressing modes
Enhanced high-precision arithmetic operation by a 32-bit accumulator
Enhanced signed multiply/divide instructions and RETI instruction function
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Enhanced interrupt function
Eight programmable priority levels
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Automatic transfer function independent of CPU
Extended intelligent I/O service using up to 16 channels
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Instruction set supporting high-level language (C) and multitasking
System stack pointer, instruction set symmetry and barrel shift instructions
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Increased execution speed: 4-byte instruction queue
Note:
The MB90460/465 series runs only in single-chip mode so only internal ROM and RAM and internal
peripheral address space can be accessed.
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2
MC-