Operation Of 16-Bit Timer - Fujitsu MB90460 Series Hardware Manual

15.6.7

Operation of 16-bit Timer

The 16-bit timer has buffer and compare clear function, which is used for motor speed
checking and abnormal detection timeout. The 16-bit timer starts counting up from
counter value "0000
■ 16-bit Timer Operation
The counter value is cleared in the following conditions:
• When an overflow has occurred.
• When a match with Compare Clear Register (CPCR) is detected.
• When "1" is written to the TCLR bit of the TCSR register during operation.
• When a write timing signal is generated and MODE bit of the TCSR is "0".
• When a position detection signal is generated and MODE bit of the TCSR is "1".
• Reset
An interrupt can be generated when the counter is cleared due to a match with Compare Clear Register.
There is no interrupt when an overflow occurs.
Note:
Word access to Compare Clear Register and Timer Buffer Register must be used.
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Interrupt
Figure 15.6-28 Clearing the Counter upon a Match with Compare Clear Register
Counter value
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Reset
Compare clear
register value
Interrupt
" after a reset has been completed and counting enable bit is set.
H
Figure 15.6-27 Clearing the Counter by an Overflow
BFFF
CHAPTER 15 MULTI-PULSE GENERATOR
Overflow
Match
H
Time
Match
Time
425