Fujitsu MB90460 Series Hardware Manual page 423

CHAPTER 15 MULTI-PULSE GENERATOR
■ Signal Flow Diagram for Reload Timer 0 or Position Detection by Setting OPS2 to
OPS0 = 100 or 101
B
Figure 15.6-10 Signal Flow Diagram for Reload Timer 0 or Position Detect (OPS2 to OPS0 = 100
16-BIT RELOAD TIMER 0
OPDBR0 WRITE SIGNAL
SNI2 to Pin
SNI0
At this setting the write signal is generated by the compare match or effective edge input of the position
detection or whenever the 16-bit reload timer 0 is underflow. The compare match is triggered by any
effective edge change in SNI2 to SNI0 pins.
■ OPDR Register Write Timing Diagram
(OPS2 to OPS0 = 001
Figure 15.6-11 OPDR Register Write Timing Diagram
OPS2 to OPS0
BNKF,
RDA2 to RDA0
(OPDR)
OPDBR1[0]
OPDBR4[0]
OPDBR7[0]
WTO
OP00
404
B
TIN
TOUT
POSITION
DETECTION
, 010 , 011 , 100
B B B
(OPS2 to OPS0 = 001
0001
TIN0O
WTIN0
OPDBR0W
WTIN1
DATA WRITE CONTROL UNIT
, 101 , 110 , 111
B B B
, 010 , 011
B B B
001 or 010 or 011 or 100 or 101 or 110 or 111
0100
TIN0
WTO
)
B
, 100 , 101 , 110 , 111
B B B
0111
or 101 )
B B
Pin TIN0
WRITE
TIMING
OUTPUT
)
B