Fujitsu MB90460 Series Hardware Manual page 588

TMRD1 EQU
;-------Main program------------------------------------------------------------------------------------------------
CODE CSEG
START:
AND
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
OR
LOOP: MOVA,#00H
MOVA,#01H
BRA
;-------Interrupt program-------------------------------------------------------------------------------------------------
ED_INT1:
MOV
RETI
CODE ENDS
;-------Vector setting------------------------------------------------------------------------------------------------------
VECT CSEG
ORG0
DSL
ORG
DSL
DB
VECT ENDS
END
000088H ;16-bit reload register 1
;Assumes that the stack pointer (SP) has already
CCR,#0BFH ;Disables interrupts
ICR00,#08H ;Interrupt level: TMCSR1:L0 (highest priority)
BAPL,#00H ;Sets the address to which conversion data is stored
BAPM,#06H ;(Uses 600H to 617H.)
BAPH,#00H ;
ISCS,#19H ;Transfers word data, adds 1 to the address,
;transfers from I/O to memory, then ends by a
;resource request
IOAL,#36H ;Sets the address of the analog data register as the
IOAH,#00H ;transfer source address pointer
DCTL,#0CH ;Transfers only channel 3 twelve times by EI
DDR5,#00000000B ;Sets P50 to P57 as input
ADER,#00001000B ;Sets P53/AN3 as analog input
ADCS0,#0DBH ;Stop conversion mode. Converts AN3 CH
ADCS1,#0A8H ;Activates the 16-bit timer, starts A/D conversion,
;Sets the timer value to 800 (320H), 100 µs
WTMRD1,#0320H
TMCSRH1,#00H ;Sets the clock source to 125 ns and disables
external trigger
TMCSRL1,#12H ;Disables timer output, disables interrupts, and
enables reload
TMCSRL1,#13H ;Activates the 16-bit reload timer 1
ILM,#07H ;Sets ILM in PS to level 7
CCR,#40H ;Enables interrupts
;Endless loop
LOOP
I:ADCS1,#80H ;Does not stop A/D conversion. Clears and disables
;Returns from interrupt
ABS=0FFH
FFD0H ;Sets vector for interrupt #11 (0BH)
ED_INT1
0FFDCH ;Sets reset vector
START
00H ;Sets single-chip mode
START
CHAPTER 20 8/10-BIT A/D CONVERTER
been initialized
and enables interrupts
the interrupt flag
2
OS
569