Fujitsu MB90460 Series Hardware Manual page 122

Figure 6.5-3 shows the operation for return to normal mode from time-base timer mode triggered by an
external reset.
Figure 6.5-3 Release of Time-base Timer Mode (by an External Reset)
Time-base timer mode
●
Return to normal mode by an interrupt
If an interrupt request higher than level 7 is issued from a peripheral circuit in time-base timer mode (when
IL2, IL1 and IL0 of the interrupt control register (ICR) are set to a value other than "111
consumption control circuit releases time-base timer mode. After the release, the CPU handles the interrupt
as it would any other interrupt. The CPU executes processing according to the settings of the I flag of the
condition code register (CCR), interrupt level mask register (ILM), and interrupt control register (ICR). If
the interrupt is accepted, the CPU executes interrupt processing. If the interrupt is not accepted, the CPU
resumes execution with the instruction that follows the instruction in which switching to time-base timer
mode was specified.
Note:
When interrupt processing is executed normally, the CPU first executes the instruction that follows
the instruction in which switching to time-base timer mode was specified. The CPU then proceeds to
interrupt processing.
RSTX pin
Main clock
PLL clock
CPU clock
Inactive
CPU operation
Time-base timer mode released.
CHAPTER 6 LOW POWER CONSUMPTION MODE
Oscillating
Oscillating
Main/PLL clock
Reset sequence Execution
Reset cleared.
"), the low power
B
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