Fujitsu MB90460 Series Hardware Manual page 16

19.4 Usage Notes on the Delayed Interrupt Generator Module ............................................................. 539
CHAPTER 20 8/10-BIT A/D CONVERTER ..................................................................... 541
20.1 Overview of the 8/10-bit A/D Converter .......................................................................................... 542
20.2 Block Diagram of the 8/10-bit A/D Converter .................................................................................. 544
20.3 8/10-bit A/D Converter Pins ............................................................................................................ 546
20.4 8/10-bit A/D Converter Registers .................................................................................................... 548
20.4.1 A/D Control Status Register 1 (ADCS1) .................................................................................. 549
20.4.2 A/D Control Status Register 0 (ADCS0) .................................................................................. 551
20.4.3 A/D Data Register (ADCR0/ADCR1) ....................................................................................... 554
20.5 8/10-bit A/D Converter Interrupts .................................................................................................... 556
20.6 Operation of the 8/10-bit A/D Converter ......................................................................................... 557
20.6.1 Conversion using EI
20.6.2 A/D Conversion Data Protection Function ............................................................................... 561
20.7 Usage Notes on the 8/10-bit A/D Converter ................................................................................... 563
20.8 Sample Program 1 for the 8/10-bit A/D Converter (Single Conversion Mode Using EI
20.9 Sample Program 2 for the 8/10-bit A/D Converter (Continuous Conversion Mode Using EI
20.10 Sample Program 3 for the 8/10-bit A/D Converter (Stop Conversion Mode Using EI
CHAPTER 21 ROM CORRECTION FUNCTION ............................................................. 571
21.1 Overview of the ROM Correction Function ..................................................................................... 572
21.2 Block Diagram of ROM Correction Function ................................................................................... 573
21.3 ROM Correction Function Registers ............................................................................................... 574
21.3.1 Program Aaddress Detection Register (PADR0/PADR1) ......................................................... 575
21.3.2 Program Address Detection Control Status Register (PACSR) ................................................ 576
21.4 Operation of the ROM Correction Function .................................................................................... 578
21.5 Example of Using ROM Correction Function .................................................................................. 579
CHAPTER 22 ROM MIRRORING FUNCTION SELECTION MODULE .......................... 583
22.1 Overview of the ROM Mirroring Function Selection Module ........................................................... 584
22.2 ROM Mirroring Function Selection Register (ROMM) .................................................................... 585
CHAPTER 23 512K / 1024K BIT FLASH MEMORY ....................................................... 587
23.1 Overview of the 512K / 1024K Bit Flash Memory ........................................................................... 588
23.2 512K / 1024K Bit Flash Memory Sector Configuration ................................................................... 589
23.3 Flash Memory Control Status Register (FMCS) ............................................................................. 590
23.4 Method of Starting the Automatic Algorithm in Flash Memory ........................................................ 592
23.5 Verifying Automatic Algorithm Execution Status ............................................................................. 593
23.5.1 Data Polling Flag (DQ7) ............................................................................................................ 595
23.5.2 Toggle Bit Flag (DQ6) ................................................................................................................ 597
23.5.3 Time limit Exceeded Flag (DQ5) .............................................................................................. 598
23.5.4 Sector Deletion Timer Flag (DQ3) ............................................................................................. 599
23.6 Detailed Explanation on the Flash Memory Write/Delete ............................................................... 600
23.6.1 Setting the Read/Reset Status .................................................................................................. 601
23.6.2 Writing the Data ......................................................................................................................... 602
23.6.3 Deleting the Data (Chip Deletion) .............................................................................................. 604
23.6.4 Deleting the Data (Sector Deletion) ........................................................................................... 605
2
OS .......................................................................................................... 560
xi
2
OS) .......... 564
2
OS) .. 566
2
OS) ............ 568