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16.4.1
PWC Control Status Register
(PWCSH0/PWCSH1, PWCSL0/PWCSL1)
The PWC control status register (PWCSH0/PWCSH1, PWCSL0/PWCSL1) controls the
PWC timer operation and reads the PWC timer state.
■ PWC Control Status Register, Upper Byte (PWCSH0/PWCSH1)
Figure 16.4-2 PWC Control Status Register (PWCSH0/PWCSH1)
Address
bit
15
STRT STOP EDIR
ch.0: 000009
H
ch.1: 000029
H
R/W
X
: Indeterminate
R/W : Read and write
: Initial value
—
: Not used
14
13
12
11
EDIE
OVIR
R/W
R
R/W
R/W
POUT
ERR
0
1
OVIE
OVIR
EDIE
EDIR
STRT STOP
10
9
8
OVIE
ERR POUT
R/W
R
R/W
0
When previous value is "1" and timer overflows
1
When previous value is "0" and timer overflows
Count result is not overwritten
Count result is overwritten before previous value is read
Overflow interrupt request enable bit
0
Disables overflow interrupt request
1
Enables overflow interrupt request
Overflow interrupt request bit
Read
0
No timer overflow
1
Timer overflows
End interrupt enable bit
0
Disables end interrupt request
1
Enables end interrupt request
End interrupt request flag bit
0
Pulse-width measurement is operating
1
Pulse-width measurement is terminated
Read
Timer stops (the timer is not
0
0
started or count ends)
0
1
No meaning
1
0
No meaning
Timer count operation in
1
1
progress (counting)
CHAPTER 16 PWC Timer
Initial value
00000000
B
Pulse output bit
Error flag bit
Operation status indication
Write
No function. Operation is not
affected
Starts or restarts the timer
(enables count)
Stops the timer operation
(disables count)
No function. The operation is not
affected
Write
Clear this bit
No effect
439
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