Fujitsu MB90460 Series Hardware Manual page 100

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System clock generation circuit
The system clock generation circuit generates an oscillation clock (HCLK) from an external oscillator
attached to it. Alternatively, an external clock can be input to this circuit.
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PLL multiplier circuit
The PLL multiplier circuit multiplies the oscillation clock through PLL oscillation and supplies a clock that
is a multiple of the frequency to the CPU clock selector.
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Clock selector
From among the main clock and four different PLL clocks, the clock selector selects the clock that is
supplied to the CPU and peripheral clock control circuits.
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Clock selection register (CKSCR)
The clock selection register is used to set switching between the oscillation clock and a PLL clock,
selection of an oscillation stabilization wait interval, and selection of a PLL clock multiplier.
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Oscillation stabilization wait interval selector
This selector selects an oscillation stabilization wait interval for the oscillation clock when stop mode is
released or when a watchdog timer reset occurs. Selection is made from among three kinds time-base timer
output. In all other cases, an oscillation stabilization wait interval is not selected.
CHAPTER 5 CLOCK
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