Table of Contents
Advertisement
3.4
Addressing
The methods for generating addresses are linear addressing and bank addressing.
In linear addressing, the complete 24-bit address is specified directly by an instruction.
In bank addressing, the upper 8 bits of the address are specified by a bank register for
the required purpose, and the lower 16 bits of the address are specified by the
instruction.
2
The F
MC-16LX family generally uses bank addressing.
■ Linear Addressing and Bank Addressing
In linear addressing, the 16-Mbyte space is accessed as consecutive address spaces. In bank addressing, the
16-Mbyte space is divided into and managed as 256 64-Kbyte banks.
Figure 3.4-1 is an overview of linear addressing and bank addressing memory management.
Figure 3.4-1 Linear Addressing and Bank Addressing Memory Management
Specified entirely by an instruction
Linear addressing
Specified by a bank register for the required purpose
Bank addressing
FF bank
64 Kbytes
FE bank
FD bank
12 bank
04 bank
03 bank
02 bank
01 bank
00 bank
Specified by an instruction
CHAPTER 3 CPU
33
Advertisement
Table of Contents
