Reset - Fujitsu MB90460 Series Hardware Manual

CHAPTER 4 RESET
4.1

Reset

If a reset cause is generated, the CPU immediately stops the current execution process
and waits for the reset to be cleared. When the reset is cleared, the CPU begins
processing at the address indicated by the reset vector.
There are four causes of a reset:
Power-on reset
Watchdog timer overflow
External reset request via the RSTX pin
Software reset request
■ Reset Causes
Table 4.1-1 lists the reset causes.
Table 4.1-1 Reset Causes
Type of reset
External pin
Software
Watchdog
timer
Power-on
MCLK: Main clock (oscillation clock frequency divided by 2)
●
External reset
An external reset is generated by the L level input to an external reset pin (RSTX pin). The minimum
required period of the L level input to the RSTX pin is 16 machine cycles (16/φ). The oscillation
stabilization wait interval is not required for external resets.
Reference:
For external reset requests via the RSTX pin, if the reset cause is generated during a write operation
(during the execution of a transfer instruction such as MOV), the CPU waits for the reset to be
cleared after the instruction is completed. The normal write operation is therefore completed even
though a reset is input concurrently.
Note, however, that waiting for the reset to be cleared may start before the transfer of the contents of
a counter specified by a string-processing instruction (such as MOVS) is completed.
66
Cause
Low level input to RSTX pin
A "0" is written to the RST bit
of the low power consumption
mode control register
(LPMCR)
Watchdog timer overflow
When the power is turned on
Watchdog
Machine clock
timer
Previous state Previous state
retained retained
Previous state Previous state
retained retained
MCLK Stop
MCLK Stop
Oscillation
stabilization
wait
No
No
Yes
Yes