Fujitsu MB90460 Series Hardware Manual page 425

F2mc-16lx 16-bit microcontroller
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CHAPTER 15 MULTI-PULSE GENERATOR
Setting the Output Data Buffer Register 0 (OPDBR0) (No. 0) as shown in Table 15.6-3 initializes the value
of the Output Data Register (OPDR). The following sequence begins to operate according to the write
timing generated:
No. 4 -> No. 6 -> No. 2 -> No. 3 -> No. 1 -> No. 5 -> No. A -> No. B -> No. 9 -> No. 4 and recycle.
The data is transferred to the Output Data Register (OPDR) sequentially. The Output Data Buffer Register
(OPDBR) is not used if it is not set, e.g. No. 7 and No. 8 in Table 15.6-3.
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