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INDEX
ROM Mirroring Function Selection Register
(ROMM) ............................................ 585
Serial Control Register (SCR0/SCR1) ................ 476
Serial Mode Register (SMR0/SMR1) ................. 478
Serial Status Register (SSR0/SSR1) ................... 480
Time-base Timer Control Register (TBTC)......... 209
Timer Buffer Register (TMBR) ......................... 389
TImer Control Ctatus Register,Lower Byte (TCCSL)
.......................................................... 297
Timer Control Status Register (TCSR) ............... 390
Timer Control Status Register,Lower Byte
(TMCSRL0/TMCSRL1) ...................... 239
Timer Control Status Register,Upper Byte (TCCSH)
.......................................................... 295
Timer Control Status Register,Upper Byte
(TMCSRH0/TMCSRH1) ..................... 237
Timer Data Register (TCDT)............................. 294
Watchdog Timer Control Register (WDTC)........ 222
Waveform Control Register (SIGCR)................. 318
Register Bank
Register Bank .................................................... 56
Register Bank Pointer
General-purpose Register Area and Register Bank
Pointer ................................................. 50
Register Bank Pointer (RP) ................................. 50
Registers
16-bit Timer Registers (TMRR0/TMRR1/TMRR2)
.......................................................... 313
Output Compare Buffer Registers (OCCPB0 to
OCCPB5) ........................................... 299
Output Compare Registers (OCCP0 to OCCP5)
.......................................................... 300
Program Address Detection Registers (×2) ......... 572
reload mode
Operation in Internal Clock Mode (reload mode)
.......................................................... 246
Reload Operation Mode
Reload Operation Mode .................................... 453
Reload Timer
16-bit Reload Timer Interrupts........................... 243
16-bit Reload Timer Interrupts and EI
16-bit Reload Timer Interrupts and EI
16-bit Reload Timer Pins .................................. 235
16-bit Reload Timer Registers ........................... 236
16-bit Reload Timer Settings ............................. 244
Baud Rates determined using the Internal Timer
(16-bit Reload Timer 0) ....................... 495
Block Diagram of the 16-bit Reload Timer ......... 233
Block Diagram of the 16-bit Reload Timer Pins
.......................................................... 235
2
OS Function of the 16-bit Reload Timer ........ 243
EI
Overview of the 16-bit Reload Timer ................. 230
Signal Flow Diagram for Reload Timer 0 and Position
Detection by Setting OPS2 to OPS0 = 011
................................................... 403
or 111
B
714
Reload Value
Request Level Setting Register
Reset
Reset Cause
Reset Causes
Reset Sequence
Reset State
Resistor
2
OS .......... 243
2
OS .......... 232
Return
Returning
Rising Edge
ROM
B
Signal Flow Diagram for Reload Timer 0 or Position
Detection by Setting OPS2 to OPS0 = 100
or 101
................................................... 404
B
Signal Flow Diagram for Reload Timer 0 Underflow
by Setting OPS2 to OPS0=001
Timing Generated by Reload Timer Underflow
......................................................... 409
Timing Generated by Reload Timer Underflow
(OPS2 to OPS0=001
Usage Notes on the 16-bit Reload Timer ............ 252
Timer Value and Reload Value ......................... 453
Request Level Setting Register (ELVR) ............. 524
Block Diagrams of the External Reset Pin ............ 69
Correspondence between Reset Cause Bits and Reset
Causes ................................................. 74
Notes about Reset Cause Bits .............................. 74
Oscillation Stabilization Wait and Reset State....... 68
Overview of Reset Operation .............................. 71
Reset Cause Bits ................................................ 73
Reset Causes ..................................................... 66
Reset Sequence................................................ 580
Setting the Read/Reset Status ............................ 601
Status of Pins during a Reset ............................... 75
Correspondence between Reset Cause Bits and Reset
Causes ................................................. 74
Notes about Reset Cause Bits .............................. 74
Reset Cause Bits ................................................ 73
Reset Causes ..................................................... 66
Reset Causes and Oscillation Stabilization Wait
Intervals ............................................... 68
Reset Sequence................................................ 580
Oscillation Stabilization Wait and Reset State....... 68
Software Pull-up Resistor ................................. 109
Stack Operations on Return from Interrupt Processing
......................................................... 150
Returning from a Hardware Interrupt ................. 129
Returning from a Software Interrupt .................. 137
Generating GATE Signal from Rising Edge of Each
RTx until 16-bit Timer 0/1/2 Underflow
when GTENx is active (DTCR0/DTCR1/
DTCR2:TMD2 to TMD0=010
ROM Area ........................................................ 30
B
............ 402
B
) ........................ 410
B
) .......... 341
B
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