Table of Contents
Advertisement
CHAPTER 11 WATCHDOG TIMER
11.3
Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) activates and clears the watchdog timer,
and displays the reset cause.
■ Watchdog Timer Control Register (WDTC)
Figure 11.3-1 shows the watchdog timer control register (WDTC). Table 11.3-1 describes the function of
each bit of the watchdog timer control register (WDTC).
bit
15
Address
0000A8
H
R: Read only
W: Write only
X: Undefined
*: Retains the previous status.
: Initial value
The interval becomes 3.5 to 4.5 times longer than the count clock (time-base timer output value) cycle. For
details, see "11.4 Operation of the Watchdog Timer".
222
Figure 11.3-1 Watchdog Timer Control Register (WDTC)
8
7
6
(TBTC)
PONR
-
R
5
4
3
2
WRST ERST SRST WTE
R
R
R
W
Interval selection bit (for 4 MHz HCLK)
WT1
WT0
Minimum
0
0
Approx. 3.58 ms
0
1
Approx. 14.33 ms
1
Approx. 57.23 ms
0
Approx. 458.75 ms Approx. 589.82 ms
1
1
HCLK: Oscillation clock
WTE
- Activation of the watchdog timer
(At first write after reset)
0
- Clearing of the watchdog timer
(At second or subsequent write after reset)
1
No operation
Reset cause bit
PONR
WRST ERST SRST
1
X
X
*
1
*
*
*
1
*
*
*
1
0
Initial value
WT1 WT0
X-XXX111
B
W
W
Interval
Oscillation clock
Maximum
Approx. 4.61 ms
2
Approx. 18.3 ms
2
Approx. 73.73 ms
2
2
Watchdog control bit
Reset cause
X
Power-on
Watchdog timer
*
External pin (RSTX input)
*
RST bit (software reset)
1
cycle count
14
11
±2
cycle
16
13
±2
cycle
18
15
±2
cycle
21
18
±2
cycle
Advertisement
Table of Contents
