Reset Cause Bits - Fujitsu MB90460 Series Hardware Manual

4.5

Reset Cause Bits

A reset cause can be identified by reading the watchdog timer control register (WDTC).
■ Reset Cause Bits
As shown in Figure 4.5-1 , a flip-flop is associated with each reset cause. The contents of the flip-flops are
obtained by reading the watchdog timer control register (WDTC). If it is necessary to identify the cause of
a reset after the reset has been cleared, the value read from the WDTC should be processed by the software
and a branch made to the appropriate program.
Power-on
detection circuit
Watchdog timer
control register
(WDTC)
S : Set
R : Reset
Q : Output :
F/F : Flip Flop
Figure 4.5-1 Block Diagram of Reset Cause Bits
RSTX Pin
RSTX = L
External reset
Power-on
request detection
circuit
S R
S R
F / F
F / F
Q
Q
2
F MC-16LX internal bus
Without periodic clear
Watchdog timer
reset detection circuit
S R S R
F / F F / F
Q Q
CHAPTER 4 RESET
RST bit set
LPMCR RST bit
write detection circuit
WDTC register
Delay
circuit
WDTC register read
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