Operation Of The Delayed Interrupt Generator Module - Fujitsu MB90460 Series Hardware Manual

CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE
19.3

Operation of the Delayed Interrupt Generator Module

When software causes the CPU to write "1" to the relevant bit of DIRR, the request latch
in the delayed interrupt generator module is set and an interrupt request is generated to
the interrupt controller.
■ Operation of the Delayed Interrupt Generator Module
When software causes the CPU to write "1" to the relevant bit of DIRR, the request latch in the delayed
interrupt generator module is set and an interrupt request is generated to the interrupt controller. If the
priority of other interrupt requests is lower than that of this interrupt or no other interrupt request is
generated, the interrupt controller generates an interrupt request to the F
16LX CPU compares the ILM bit of the internal CCR register and the interrupt request. When the request
level is higher than that of the ILM bit, the CPU starts the hardware interrupt processing microprogram
immediately after execution of the current instruction ends. As a result, the interrupt processing routine for
this interrupt is executed. This interrupt cause is cleared and task switching is done by writing "0" to the
relevant bit of DIRR in the interrupt processing routine. Figure 19.3-1 Operation of the delayed interrupt
generator module shows the operation of the delayed interrupt generator module.
Figure 19.3-1 Operation of the Delayed Interrupt Generator Module
Delayed interrupt generation module
DIRR
538
Delayed interrupt controller
WRITE
Other requests
ICR yy
ICR xx
2
MC-16LX CPU. The F
2
F MC-16LX CPU
IL
CMP
ILM
NTA
2
MC-
CMP