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CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ 16-bit Input Capture Interrupts
Table 14.5-5 lists the interrupt control bits and interrupt causes of the 16-bit input capture.
Table 14.5-5 Interrupt Control Bits and Interrupt Causes of the 16-bit Input Capture 0 to 3
Interrupt request flag bit
Interrupt request enable bit
Interrupt cause
In the 16-bit input capture, the ICP0 to ICP3 bit of the input capture control register (PICSL01/ICSL23) is
set to "1" when valid edge is detected in IN0 to IN3. If an interrupt request is enabled (PICSL01/
ICSL23:ICE0/ICE1 = 1) in this operation, the interrupt request is output to the interrupt controller.
■ 16-bit Input Capture Interrupts and EI
Table 14.5-6 lists the 16-bit input capture interrupts and EI
Table 14.5-6 16-bit Input Capture Interrupts and EI
Channel
*1
Input capture 0/1
*2
Input capture 2/3
*1: The same interrupt control register as that for 16-bit input capture 0/1 is assigned to 16-bit free-run timer compare clear.
*2: The same interrupt control register as that for 16-bit input capture 2/3 is assigned to Time-base timer.
■ Waveform Generator Interrupts
lists the interrupt control bits and interrupt causes of the waveform generator.
Table 14.5-7 Interrupt Control Bits and Interrupt Causes of the Waveform Generator
Interrupt request flag bit
Interrupt request enable bit
Interrupt cause
In the waveform generator, the TMIF bit of the 16-bit timer control register (DTCR0/DTCR1/DTCR2) is
set to "1" when 16-bit timer underflow and DTCR0/DTCR1/DTCR2:TMD2 to TMD0=000
interrupt request is enabled (DTCR0/DTCR1/DTCR2:TMIE = 1) in this operation, the interrupt request is
output to the interrupt controller.
322
16-bit input capture 0/1
PICSL01:ICP0/ICP1
PICSL01:ICE0/ICE1
Valid edge is detected in IN0/IN1
Interrupt control register
Interrupt
number
Register
name
#33 (21
)
ICR11
H
#35 (23
)
ICR12
H
2
OS
2
OS.
2
OS
Address
Lower
0000BB
FFFF78
H
0000BC
FFFF70
H
Waveform generator
16-bit timer 0/1/2
DTCR0/DTCR1/DTCR2:TMIF
DTCR0/DTCR1/DTCR2:TMIE
16-bit timer 0/1/2 underflow
16-bit input capture 2/3
ICSL23:ICP2/ICP3
ICSL23:ICE2/ICE3
Valid edge is detected in IN2/IN3
Vector table address
Middle
Upper
FFFF79
FFFF7A
H
H
FFFF71
FFFF72
H
H
DTTI0
SIGCR:DTIF
--
Low level is detected in DTTI0
B
2
EI
OS
H
O
H
or 001
. If an
B
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