Timer Control Status Register 0 To 2 (Tmcsr0 To Tmcsr2) - Fujitsu F2MC-16LX Hardware Manual

16.2.1

Timer Control Status Register 0 to 2 (TMCSR0 to TMCSR2)

Configuration and functions of timer control status registers 0 to 2 (TMCSR0 to
TMCSR2) are described.
Timer Control Status Register 0 to 2 (TMCSR0 to TMCSR2)
The timer control status registers 0 to 2 (TMCSR0 to TMCSR2) control the operation mode and interrupt of
16-bit reload timer. Bits other than UF/CNTE/TRG are modified at CNTE=0.
Figure 16.2-2 shows the bit configuration of timer control status registers 0 to 2 (TMCSR0 to TMCSR2).
Figure 16.2-2 Bit Configuration of Timer Control Status Registers 0 to 2 (TMCSR0 to TMCSR2)
Address:
ch0 : 000063
H
ch1 : 000067
H
ch2 : 00006B
H
Address:
ch0 : 000062
H
ch1 : 000066
H
ch2 : 00006A
H
R/W Readable/Writable
Undefined value
X
Undefined
The functions of each bit of timer control status registers 0 to 2 (TMCSR0 to TMCSR2) are described in
the following:
[bit 15 to bit 12] Undefinition bit
The reading value is irregular. No effect on writing.
[bit 11, bit 10] CSL1, CSL0 (clock selection)
Clock source is selected by count clock selection.
CSL1
0
0
1
1
12
15 14 13
(X) (X) (X) (X)
7 6 5 4
MOD0 OUTE OUTL RELD INTE
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
CSL0
0
1
0
1
11 10 9 8
CSL1 CSL0 MOD2 MOD1
(R/W) (R/W) (R/W) (R/W)
3 2 1 0
CNTE TRG
UF
Clock source (machine clock f=24 MHz time)
φ/2 (0.083 µs) [Initial value]
1
φ/2 3 (0.33 µs)
φ/2 5 (1.33 µs)
Event count mode
CHAPTER 16 16-BIT RELOAD TIMER
TMCSR 0 to TMCSR 2 (upper)
Initial value
XXXX0000
B
TMCSR 0 to TMCSR 2 (lower)
Initial value
00000000
B
389