Fujitsu MB90460 Series Hardware Manual page 729

INDEX
Output Compare
16-bit Output Compare (×6) .............................. 280
16-bit Output Compare Interrupts ...................... 321
16-bit Output Compare Interrupts and EI
16-bit Output Compare Operation ...................... 332
16-bit Output Compare Registers ....................... 290
16-bit Output Compare Timing.......................... 336
Block Diagram of 16-bit Output Compare .......... 284
Sample Program for 16-bit Output Compare ....... 352
Usage Notes on the 16-bit Output Compare ........ 349
Output Compare Buffer Registers
Output Compare Buffer Registers
(OCCPB0 to OCCPB5)........................ 299
Output Compare Registers
Output Compare Registers (OCCP0 to OCCP5)
.......................................................... 300
Output Condition
Output Condition of RTO0 to RTO5 and GATE
.......................................................... 339
Output Control Lower Register
Output Control Lower Register (OPCLR) ........... 374
Output Control Upper Register
Output Control Upper Register (OPCUR) ........... 372
Output Data Buffer Lower Register
Output Data Buffer Lower Register (OPDBR)
.......................................................... 382
Output Data Buffer Register
Operation of Output Data Buffer Register........... 405
Output Data Buffer Upper Register
Output Data Buffer Upper Register (OPDBR)
.......................................................... 380
Output Data Lower Register
Output Data Lower Register (OPDR) ................. 378
Output Data Register
Operation of Data Transfer of Output Data Register
.......................................................... 407
Output Data Register (OPDR) ........................... 398
Output Data Register (SODR0/SODR1) ............. 482
Output Data Register Block Diagram ................. 397
Output Data Upper Register
Output Data Upper Register (OPDR) ................. 376
Output Pulse
PPG0 Output Pulse from Rising Edge of RT to 16-bit
Timer Underflow (DTCR0/DTCR1/
DTCR2:TMD2 to TMD0=010
Output Waveform
OPTx Output Waveform Timing Diagram
(WTS1,WTS0=00
Overlap
Making Non-overlap Signals by using PPG in Inverted
Polarity (DTCR0/DTCR1/DTCR2:TMD2 to
)...................................... 346
TMD0=111
B
710
2
OS ...... 321
)........... 342
B
) ............................ 398
B
Making Non-overlap Signals by using PPG in Normal
Polarity (DTCR0/DTCR1/DTCR2:TMD2 to
) ..................................... 345
TMD0=111
B
Making Non-overlap Signals by using RT1/RT3/RT5
in Inverted Polarity (DTCR0/DTCR1/
DTCR2:TMD2 to TMD0=100
Making Non-overlap Signals by using RT1/RT3/RT5
in Normal Polarity (DTCR0/DTCR1/
DTCR2:TMD2 to TMD0=100
P
Package Dimensions
DIP-64P-M01 Package Dimensions ..................... 11
FPT-64P-M06 Package Dimensions .................... 12
FPT-64P-M09 Package Dimensions .................... 13
PACSR
Program Address Detection Control Status Register
(PACSR)............................................ 576
PADR
Program Address Detection Register 0/1
(PADR0/PADR1) ............................... 575
PC
Program Counter (PC) ........................................ 52
PCB
Bank Registers (PCB,DTB,USB,SSB,ADB)......... 54
Bank Select Prefixes (PCB,DTB,ADB,SPB) ........ 58
PCNTH
PPG Control Status Register,Upper Byte
(PCNTH0 to PCNTH2) ....................... 267
PCNTL
PPG Control Status Register,Lower Byte
(PCNTL0 to PCNTL2) ........................ 269
PCSR
PPG Period Setting Buffer Register
(PCSR0 to PCSR2) ............................. 265
PDCR
PPG Down Counter Register (PDCR0 to PDCR2)
......................................................... 264
PDUT
PPG Duty Setting Buffer Register (PDUT0 to PDUT2)
......................................................... 266
period
Calculating Pulse Width/period ......................... 457
Pulse Width/period Measurement Range ............ 457
PICSH
PPG Output Control/Input Capture Control Status
Register,Upper Byte (PICSH01)........... 309
PICSL
Input Capture Control Status Register,Lower Byte
(PICSL01).......................................... 311
Pin Functions
I/O Pins and Pin Functions.................................. 14
PLL Clock Mode
Main Clock Mode and PLL Clock Mode .............. 84
) .......... 344
B
) .......... 343
B