Fujitsu MB90460 Series Hardware Manual page 520

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Reception operation
Reception operation is performed every time it is enabled (SCR0/SCR1: RXE = 1). When a start bit is
detected, a frame of data is received according to the data format specified by the control register (SCR0/
SCR1). After the frame has been received, the error flag is set if an error occurs, then the receive data full
flag bit (SSR0/SSR1: RDRF) is set to "1". At this point, a reception interrupt request is output if it is
enabled (SSR0/1: TIE = 1).
Check each flag of the input data register (SIDR0/SIDR1). If the reception is normal, read the input data
register (SIDR0/SIDR1). If an error is found, proceed to error handling. The RDRF flag is cleared to "0"
every time receive data is read from SIDR0/SIDR1.
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Stop bit
For transmission, 1 or 2 bits can be selected. During reception however, the first bit is the only one that is
always checked.
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Error detection
• In mode 0, parity, overrun and framing errors can be detected.
• In mode 1, overrun and framing errors can be detected but parity errors cannot be detected.
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Parity 0
Parity can only be used in operation mode 0 (asynchronous, normal mode). Whether to provide parity can
be specified using the PEN bit of the control register (SCR0/SCR1). Even or odd parity can also be
specified using the P bit of the control register (SDR0/SDR1). In operation mode 1 (asynchronous,
multiprocessor mode) and operation mode 2 (synchronous, normal mode), parity cannot be used. Figure
17.7-2 shows both transmission and receive data when parity is enabled.
Figure 17.7-2 Transmission Data when Parity is enabled
SIN0/SIN1
SOT0/SOT1
SOT0/SOT1
ST : Start bit
SP : Stop bit
Note : Parity is disabled in operation modes 1 and 2
ST
1 0 1 1 0 0 0
ST
1 0 1 1 0 0 1
ST
1 0 1 1 0 0 0
Data Parity
A parity error occurs
during reception with even parity
SP
(SCR0/SCR1: P=0)
Transmission with even parity
(SCR0/SCR1: P=0)
SP
Transmission with odd parity
(SCR0/SCR1: P=1)
SP
CHAPTER 17 UART
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