Time-Base Timer Control Register (Tbtc) - Fujitsu MB90460 Series Hardware Manual

10.3

Time-base Timer Control Register (TBTC)

The time-base timer control register (TBTC) selects the interval, clears the counter,
controls interrupts, and checks the status.
■ Time-base Timer Control Register (TBTC)
bit 15
Address
RESV
0000A9
H
R/W
R/W: Read/write
W: Write only
- : Not used
x : Undefined
Initial value
Figure 10.3-1 Time-base Timer Control Register (TBTC)
14 13 12 11
- - TBIE TBOF TBR TBC1 TBC0
R/W R/W
10 9 8 7
(WDTC)
W R/W R/W
TBC1 TBC0
12
0 0 2 /HCLK (Approx. 1.0 ms)
14
0 1
2 /HCLK (Approx. 4.1 ms)
16
1 0
2 /HCLK (Approx. 16.4 ms)
19
1 1
2 /HCLK (Approx. 131 ms)
Values in parentheses are for a 4 MHz oscillation clock.
Time-base timer initialization bit
TBR
During reading
0 -
1 The read value is always "1".
Interrupt request flag bit
TBOF
During reading
No overflow from the
0
specified bit
Overflow from the specified
1
bit
Interrupt request enable bit
TBIE
0 Interrupt request output disabled
1 Interrupt request output enabled
RESV
Always write "1" to this bit.
CHAPTER 10 TIME-BASE TIMER
0
Initial value
1XX00100
B
Interval selection bit
During writing
Clearing of the time-base timer
counter and TBOF bit
No change, no effect on other bits.
During writing
Clearing of this bit
No change, no effect on other bits.
Reserved bit
209