Fujitsu MB90460 Series Hardware Manual page 390

(Continued)
Compare Clear Register (Upper)
Address:
003FFB
Read/Write
Initial Value
Compare Clear Register (Lower)
Address:
003FFA
Read/Write
Initial Value
Timer Buffer Register (Upper)
Address: 003FFD
Read/Write
Initial Value
Timer Buffer Register (Lower)
Address: 003FFC
Read/Write
Initial Value
Timer Control Status Register
Address: 00008F
Read/Write
Initial Value
Noise Cancellation Control Register
Address: 00008E
Read/Write
Initial Value
15
bit 14
_
CL15 CL14 CL13
H
R/W R/W R/W
X
X X
6
bit 7
CL07 CL06 CL05
H
R/W R/W
R/W
X
X
bit 15 14
T15 T13
T14
H
R
R
R
0 0
0
6
7
bit
T07 T06 T05
H
R R
0
0
bit
15
14
S21
S20 S11
H
R/W
R/W R/W
0
0 0
6
bit
7
TCLR MODE ICLR
H
R/W R/W
R/W
0
0
CHAPTER 15 MULTI-PULSE GENERATOR
13
12 11
CL12 CL11 CL10
R/W R/W R/W
X X
X
3
5 4
CL04 CL03 CL02
R/W R/W R/W
X X X X
11
13 12
T12 T11 T10
R
R R
0 0 0
5 3
4
T04 T03 T02
R R R
R
0 0 0
0
13 11
12
S10 S01 S00
R/W R/W
R/W
0
0 0
5 3
4
ICRE TMEN CLK2
R/W R/W R/W
0 0 0
0
9
10
8
CL09 CL08
R/W R/W
X X
0
2 1
CL01 CL00
R/W
R/W
X
X
9 8
10
T09 T08
R
R
0
0
0
2 1
T01 T00
R R
0 0
9
10 8
D1 D0
R/W
R/W
0
0
2 1 0
CLK1 CLK0
R/W R/W
0 0
CPCR
CPCR
TMBR
TMBR
NCCR
TCSR
371