Fujitsu MB90460 Series Hardware Manual page 389

CHAPTER 15 MULTI-PULSE GENERATOR
(Continued)
Output Data Buffer Registers (Upper)
Addresses:
003FF7 to E1
H H
(Odd Addresses)
Read/Write
Initial Value
Output Data Buffer Registers (Lower)
Addresses:
003FF6 to E0
H H
(Even Addresses)
Read/Write
Initial Value
Input Control Register (Upper)
Address: 00008D
H
Read/Write
Initial Value
Input Control Register (Lower)
Address: 00008C
H
Read/Write
Initial Value
370
bit 15 13
14
_
BNKF RDA2 RDA1 RDA0
R/W R/W R/W R/W
0
0 0
6
7
bit
OP31 OP30 OP21 OP20
R/W
R/W R/W
0
0
0
15 14 13
bit
WTS1 CPIF CPIE
WTS0
R/W
R/W R/W R/W
0 0
0
6
bit 7
CPE1 CPE0 SNC2 SNC1 SNC0 SEE2
R/W R/W
R/W
0
0
0
12 11 10
OP51 OP50 OP41 OP40
R/W R/W R/W
0 0
0 0
5 3
4 2
OP11 OP10 OP01 OP00
R/W
R/W R/W
0
0 0
11
12
10
CPD2 CPD1 CPD0 CMPE
R/W
R/W
R/W
0 0 0
0
3
5
4
SEE1 SEE0
R/W R/W R/W
0 0
0
9
8
OPDBRB to
OPDBR0
R/W
0
0
1
OPDBRB to
OPDBR0
R/W
R/W
0
0
9 8
IPCUR
R/W
0
2 1 0
IPCLR
R/W R/W
0 0
(Continued)