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Table 17.4-3 Functions of Each Bit of Status Register (SSR0/SSR1)
Bit name
PE:
bit15
Parity error flag bit
ORE:
bit14
Overrun error flag bit
FRE:
bit13
Framing error flag bit
RDRF:
bit12
Receive data full flag
bit
TDRE:
bit11
Transmission data
empty flag bit
BDS:
bit10
Transfer direction
selection bit
RIE:
bit9
Reception interrupt
request enable bit
TIE:
bit8
Transmission interrupt
request enable bit
• This bit is set to "1" when a parity error occurs during reception and is cleared when
"0" is written to the RFC bit of the mode control register (SMR0/SMR1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in input data register (SIDR0/SIDR1) is invalid when this flag is set.
• This bit is set to "1" when an overrun error occurs during reception and is cleared
when "0" is written to the RFC bit of the mode control register (SMR0/SMR1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the input data register (SIDR0/SIDR1) is invalid when this flag is set.
• This bit is set to "1" when a framing error occurs during reception and is cleared
when "0" is written to the RFC bit of the mode control register (SMR0/SMR1).
• A reception interrupt request is output when this bit and the RIE bit are "1".
• Data in the input data register (SIDR0/SIDR1) is invalid when this flag is set.
• This flag indicates the status of the input data register (SIDR0/SIDR1).
• This bit is set to "1" when receive data is loaded into SIDR0/SIDR1 and is cleared
to "0" when input data register SIDR0/SIDR1 is read.
• A reception interrupt request is output when this bit and the RIE bit are "1".
• This flag indicates the status of output data register (SODR0/SODR1).
• This bit is cleared to "0" when transmission data is written to SODR0/SODR1 and
is set to "1" when data is loaded into the transmission shift register and transmission
starts.
• A transmission interrupt request is output when this bit and the RIE bit are "1".
(Note)
This bit is set to "1" (SODR0/SODR1 empty) as its initial value.
• This bit selects whether to transfer serial data from the least significant bit (LSB
first, BDS = 0) or the most significant bit (MSB first, BDS = 1).
(Note)
The high-order and low-order sides of serial data are interchanged with each other
during reading from or writing to the serial data register. If this bit is set to another
value after the data is written to the SDR register, the data becomes invalid.
• This bit enables or disables input of a request for transmission interrupt to the CPU.
• A reception interrupt request is output when this bit and the receive data flag bit
(DRRF) are 1 or this bit and one or more error flag bits (PE, ORE and FRE) are "1".
• This bit enables or disables output of a request for transmission interrupt to the
CPU.
• A transmission interrupt request is output when this bit and the TDRE bit are "1".
CHAPTER 17 UART
Function
481
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