Fujitsu MB90460 Series Hardware Manual page 304

■ Block Diagram of Waveform Generator
φ
Divider
DTCR0
RT0
RT1
DTCR1
RT2
RT3
DTCR2
RT4
RT5
Figure 14.2-5 Waveform Generator Block Diagram
DCK2 DCK1 DCK0 NRSL DTIF DTIE
PICSH01 PGEN1 PGEN0
TMD2 TMD1 TMD0 GTEN1 GTEN0
16-bit timer 0 Compare circuit
16-bit timer register 0
TMD2 TMD1 TMD0 GTEN1 GTEN0
PICSH01 PGEN3 PGEN2
16-bit timer 1 Compare circuit
16-bit timer register 1
TMD2 TMD1 TMD0 GTEN1 GTEN0
PICSH01 PGEN5 PGEN4
16-bit timer 2 Compare circuit
16-bit timer register 2
CHAPTER 14 MULTI-FUNCTIONAL TIMER
NWS1 NWS0
DTTI0 control circuit
GATE 0/1
TO0
Waveform control
TO1
Selector
Selector
U
Dead time generator
X
GATE 2/3
TO2
Waveform control
TO3
Selector
Selector
V
Dead time generator
Y
GATE 4/5
TO4
Waveform control
TO5
Selector
Selector
W
Dead time generator
Z
SIGCR
DTTI0
Noise cancellation
GATE
(to PPG0)
RTO0 (U)
RTO1 (X)
RTO2 (V)
RTO3 (Y)
RTO4 (W)
RTO5 (Z)
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