Fujitsu MB90460 Series Hardware Manual page 319

CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Output Compare Registers (OCCP0 to OCCP5)
Output Compare Register (Upper)
Address: ch.0 000071
ch.1 000073
ch.2 000075
ch.3 000077
ch.4 000079
ch.5 00007B
Read/write
Initial value
Output Compare Register (Lower)
Address: ch.0 000070
ch.1 000072
ch.2 000074
ch.3 000076
ch.4 000078
ch.5 00007A
Read/write
Initial value
The output compare register is a 16-bit register which is used to compare the count value of 16-bit free-run
timer. The initial value of the output compare register is undetermined, so output compare buffer register
(OCCPB) must be set with a value before enabling the operation.
When the value of the output compare register matches the count value of 16-bit free-run timer, a compare
signal is generated to set the output compare interrupt flag (OCS0/OCS2/OCS4:IOP0/IOP1). If output level
is set (OCS1/OCS3/OCS5:OTD0/OTD1), the output level of RT0 to RT5 corresponding to the output
compare register (OCCP0 to OCCP5) can be reversed.
Word access to this register is recommended.
300
Figure 14.4-11 Output Compare Registers (OCCP0 to OCCP5)
H
H
bit 15 14
H
H
H
OP15 OP14 OP13 OP12
H
R R
X X
H
H
bit
7
H
H
H
OP07 OP06 OP05 OP04
H
R R
X X
13 12 11
OP11 OP10
R R R R
X X X X
6 5 4 3
OP03 OP02
R R R
X X X
10 9 8
OP09 OP08
R R
X
X
2 1 0
OP01 OP00
R R R
X X X
OCCP0 to
OCCP5
OCCP0 to
OCCP5