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11.2
Configuration of the Watchdog Timer
The watchdog timer consists of the following five blocks:
• Count clock selector
• Watchdog counter (2-bit counter)
• Watchdog reset generator
• Counter clear control circuit
• Watchdog timer control register (WDTC)
■ Block Diagram of the Watchdog Timer
Figure 11.2-1 shows the block diagram of the watchdog timer.
Start of sleep mode
Start of hold status mode
Start of stop mode
One-half of HCLK
HCLK: Oscillation clock
●
Count clock selector
This circuit is used to select the count clock of the watchdog timer from four types of time-base timer
outputs. This determines the watchdog reset generation time.
●
Watchdog counter (2-bit counter)
This 2-bit up counter uses the time-base timer output as the count clock.
●
Watchdog reset generator
Used to generate the reset signal by an overflow of the watchdog counter.
●
Counter clear circuit
Used to clear the watchdog counter and to control the operation or stopping of the counter.
●
Watchdog timer control register (WDTC)
Used to activate or clear the watchdog timer; holds the reset generation cause.
Figure 11.2-1 Block diagram of the watchdog timer
Watchdog timer control register (WDTC)
Watchdog timer
Counter
Count
clear control
clock
circuit
selector
Clear
(Time-base timer counter)
CHAPTER 11 WATCHDOG TIMER
Activation
with CLR
Over-
2-bit
Watchdog
flow
counter
reset generator
To the internal
reset generator
221
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