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CHAPTER 3 CPU
3.9.4
Restrictions on Prefix Codes
The following three restrictions are imposed on the use of prefix codes:
• Interrupt/hold requests are not accepted during the execution of prefix codes and
interrupt/hold suppression instructions.
• If a prefix code is placed before an interrupt/hold instruction, the effect of the prefix
code is delayed.
• If consecutively placed prefix codes conflict, the last prefix code is valid.
■ Prefix Codes and Interrupt/hold Suppression Instructions
Table 3.9-6 lists the interrupt/hold suppression instructions and prefix codes that have restrictions.
Table 3.9-6 Prefix Codes and Interrupt/hold Suppression Instructions
Instructions that do not
accept interrupt and
hold requests
●
Interrupt/hold suppression
As shown in Figure 3.9-1, an interrupt or hold request generated during the execution of prefix codes and
interrupt/hold instructions is not accepted. The interrupt/hold is not processed until the first instruction that
is not governed by a prefix code or that is not an interrupt/hold suppression instruction is executed.
62
Prefix codes
PCB
DTB
ADB
SPB
CMR
NCC
Figure 3.9-1 Interrupt/hold Suppression
Interrupt/hold suppression instruction
............
↑
Interrupt request generated
Interrupt/hold suppression instructions
(instructions that delay the effect of prefix codes)
MOV
OR
AND
POPW
(a) Ordinary instruction
......
(a)
↑
Interrupt accepted
ILM, #imm8
CCR, #imm8
CCR, #imm8
PS
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