Fujitsu MB90460 Series Hardware Manual page 569

CHAPTER 20 8/10-BIT A/D CONVERTER
Table 20.4-1 A/D Dontrol Status Register 1 (ADCS1)
Bit name
BUSY:
bit15
Busy bit
INT:
Interrupt
bit14
request flag
bit
INTE:
Interrupt
bit13
request
enable bit
PAUS:
bit12
Halt flag bit
STS1, STS0:
bit11, A/D
bit10 activation
select bit
STRT:
A/D
bit9
conversion
activation bit
RESV:
bit8
Reserved bit
550
• This bit indicates the operating status of the A/D converter.
• If the value read from this bit is "0", A/D conversion has halted. If the read value is "1",
A/D conversion is in progress.
• Writing "0" to this bit forces the A/D conversion to stop. Writing "1" to this bit does not
change the bit value and has no effect on other bits.
(Note)
Never select forced stop (BUSY = 0) and software activation (STRT = 1) simultaneously.
• When A/D conversion data is set in the A/D data register, this bit is set to "1".
• When both this bit and the interrupt request enable bit (ADCS: INTE) are "1", an
interrupt request is generated. If EI²OS has been enabled, it is activated.
• Writing "0" to this bit clears the bit. Writing "1" to this bit does not change the bit value
and has no effect on other bits.
• When EI²OS is activated, this bit is cleared.
(Note)
When clearing this bit by writing "0" it, do so only while the A/D converter is not
operating.
• This bit enables or disables interrupt output to the CPU.
• When both this bit and the interrupt request flag bit (ADCS: INT) are set to "1", an
interrupt request is generated.
• When EI²OS is used, set this bit to "1".
• When A/D conversion stops temporarily, this bit is set to "1".
• This A/D converter has just one A/D data register. In continuous conversion mode, if a
conversion result were written before the previous conversion result was read by the CPU,
the previous result would be lost. When continuous conversion mode is selected, the
program must be written so that the conversion result is automatically transferred to
memory by EI²OS each time a conversion is completed. This bit also protects against
multiple interrupts preventing the completion of conversion data transfer before the next
conversion. When a conversion is completed, this bit is set to "1". This status is
maintained until EI²OS finishes transferring the contents of the data register. Meanwhile,
the A/D conversion is halted so that no conversion data can be stored. When EI²OS
completes the transfer, the A/D converter automatically resumes the conversion.
(Note)
This bit is valid only when EI²OS is used.
• These bits select how A/D conversion is to be activated.
• When two or more activation causes are shared, activation is the result of the cause that
occurs first.
(Note)
Change the setting during A/D conversion only while there is no corresponding activation
cause, since the change becomes effective immediately.
• This bit allows software to start A/D conversion.
• Writing "1" to this bit activates A/D conversion.
• In stop conversion mode, conversion cannot be reactivated with this bit.
• In byte/word instruction, "1" is read.
• In read-modify-write instruction, "0" is read.
(Note)
Never select forced stop (BUSY = 0) and software activation (STRT = 1)
simultaneously.
(Note)
Always write "0" to this bit.
Function