Fujitsu MB90460 Series Hardware Manual page 449

CHAPTER 15 MULTI-PULSE GENERATOR
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Notes about interrupts
• When the DTIF bit of the output control upper register (OPCUR) is set to "1", control cannot be
returned from interrupt processing. Always clear the DTIF bit.
• When the WTIF bit of the output control upper register (OPCUR) is set to "1", control cannot be
returned from interrupt processing. Always clear the WTIF bit.
• When the PDIF bit of the output control lower register (OPCLR) is set to "1", control cannot be returned
from interrupt processing. Always clear the PDIF bit.
• When the CPIF bit of the input control upper register (IPCUR) is set to "1", control cannot be returned
from interrupt processing. Always clear the CPIF bit.
• Since the above interrupts share an interrupt vector with other resource, interrupt causes must be
checked carefully by the interrupt processing routine when interrupts are used.
Also, when EI
■ Usage Notes on the 16-bit Timer
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Notes about using a program for setting
• Word access to compare clear register (CPCR) and timer buffer register (TMBR) must be used.
• Before the prescaler clock is changed, the timer counter should be disable first by setting the TMEN bit
to "0". Change the CLK2, CLK1 and CLK0 bits of the timer control status register (TCSR) only when
the timer is not counting.
• If the compare clear register (CPCR) is loaded a value same as the timer counter value at that moment,
the comparison operation will NOT be performed until next same counter value.
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Notes about interrupts
• When the ICLR bit of the timer control status register (TCSR) is set to "1" and an interrupt request is
enabled (TCSR: ICRE = 1), control cannot be returned from interrupt processing. Always clear the
ICLR bit.
• Since the 16-bit timer shares an interrupt vector with other resource, interrupt causes must be checked
carefully by the interrupt processing routine when interrupts are used.
Also, when EI
430
2
OS is used by these interrupts, shared resource interrupts must be disabled.
2
OS is used by the 16-bit timer, shared resource interrupts must be disabled.