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CHAPTER 3 CPU
3.7.4
Condition Code Register (PS: CCR)
The condition code register (CCR) is an 8-bit register that consists of the bits that
indicate the results of an arithmetic operation and the contents of transfer data and bits
that control interrupt request acceptance.
■ Condition Code Register (CCR) Configuration
Figure 3.7-9 shows the configuration of the CCR register. Refer to the programming manual for details
about the status of the condition code register (CCR) during instruction execution.
Default value ⇒
Interrupt enable flag
●
Interrupt enable flag (I)
In response to all interrupt requests other than software interrupts, when the I flag is "1", interrupts are
enabled. When the I flag is "0", interrupts are disabled. Cleared by a reset.
●
Stack flag (S)
This flag indicates the pointer used for a stack operation.
When the S flag is "0", the user stack pointer (USP) is valid. When the S flag is "1", the system stack
pointer (SSP) is valid. Set when an interrupt is accepted or when a reset occurs.
●
Sticky bit flag (T)
Set to "1" when the data shifted out by the carry contains at least one 1 during execution of a logical right
shift instruction or arithmetic right shift instruction. Otherwise, set to "0". Also set to "0" when the shift
amount is zero.
●
Negative flag (N)
Set to "1" when the MSB is ""1 as the result of an arithmetic calculation. Cleared to "0 "when the MSB is
"0".
●
Zero flag (Z)
Set to "1" when the result of an arithmetic calculation is all zeros. Otherwise, set to "0".
48
Figure 3.7-9 Condition Code Register (CCR) Configuration
bit
7
6
–
I
–
0
Stack flag
Sticky flag
Negative flag
Zero flag
Overflow flag
Carry flag
5
4
3
2
1
0
S
T
N
Z
V
C
1
x
x
x
x
x
: CCR
- : Not used
x : Undefined
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