Port 5 Registers (Pdr5, Ddr5 And Ader) - Fujitsu MB90460 Series Hardware Manual

9.8.1

Port 5 Registers (PDR5, DDR5 and ADER)

This section describes the port 5 registers.
■ Functions of Port 5 Registers
●
Port 5 data register (PDR5)
The PDR5 register indicates the state of each pin of port 5.
●
Port 5 data direction register (DDR5)
The DDR5 register specifies the direction of a data flow (input or output) at each pin (bit) of port 5. When
a DDR5 register bit is "1", the corresponding port (pin) is set as an output port. When the bit is "0", the
port (pin) is set as an input port.
●
Analog input enable register (ADER)
Each bit of the ADER register specifies whether the corresponding port 5 pin is to be used as a general-
purpose I/O port or an analog input pin. Setting an ADER bit to "1" enables the corresponding pin for
analog input. Setting the bit to "0" enables the pin for general-purpose I/O.
Note:
If a signal at an intermediate level is input in port I/O mode, input leak current flows. Therefore, for a
pin used for analog input, be sure to set the corresponding ADER bit to "1" for analog input.
Reference:
When the CPU is reset, the DDR5 register is reset to "0" and the ADER register is set to "1" for
analog input.
Table 9.8-3 lists the functions of the port 5 registers.
Table 9.8-3 Port 5 Register Functions
Register Data
0
Port 5 data
register (PDR5)
1
0
Port 5 data
direction
register (DDR5)
1
Analog input 0
enable register
1
(ADER)
R/W: Read/write enabled
X : Undefined
During
reading
The pin is at
the low level.
The pin is at
the high level.
The direction The output buffer is turned off to
latch is "0". place the port in input mode.
The direction The output buffer is turned on to
latch is "1". place the port in output mode.
Port I/O mode
Analog input mode
During writing
CHAPTER 9 I/O PORT
Read/
Address Initial value
Write
000005 XXXXXXX
R/W
H
000015 00000000
R/W
H
000017 11111111
R/W
H
B
B
B
195