Fujitsu MB90460 Series Hardware Manual page 482

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Notes about interrupts
• When the OVIR bit of the PWC control status register (PWCSH0/PWCSH1) is set to "1" and an
interrupt request is enabled (PWCSH0/PWCSH1:OVIE = 1), control cannot be returned from interrupt
processing. Always clear the OVIR bit.
• When the EDIR bit of the PWC control status register (PWCSH0/PWCSH1) is set to "1" and an
interrupt request is enabled (PWCSH0/PWCSH1:EDIE = 1), control cannot be returned from interrupt
processing. Always clear the OVIR bit.
• Since the PWC timer shares an interrupt vector with other resource, interrupt causes must be checked
carefully by the interrupt processing routine when interrupts are used.
Also, when EI
2
OS is used by the PWC timer, shared resource interrupts must be disabled.
CHAPTER 16 PWC Timer
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