Fujitsu MB90460 Series Hardware Manual page 98

■ Clock Supply Map
Since the machine clock generated in the clock generation block is supplied as the clock that controls
operation of the CPU and peripheral functions, the operation of the CPU and peripheral functions is
affected by switching of the main clock and the PLL clock (clock mode) and a change in the PLL clock
multiplier.
Since some peripheral functions receive frequency-divided output from the time-base timer, a peripheral
unit can select the clock best suited for its operation. Figure 5.1-1 shows the clock supply map.
Clock generation block
X0
Pin System
clock
X1
generation
Pin
circuit
Machine clock
Figure 5.1-1 Clock Supply Map
Time-base timer
1 2 3 4
PLL multiplier circuit
PCLK
Divide-by-2
Clock selecter
HCLK
MCLK
Peripheral function
4
Watchdog timer
16-bit PPG
timer 0
16-bit PPG
timer 1
16-bit PPG
timer 2
16-bit reload
timer 0
UART0
UART1
CPU
16-bit reload
timer 1
Waveform
generator
16-bit output compare
(Ch.0 to Ch.5)
16-bit free-run
timer
16-bit input capture
(Ch.0 to Ch.3)
8/10-bit A/D
converter
Waveform
sequencer
PWC (Ch.0 to Ch.1)
3
Oscillation stabilization
wait control
CHAPTER 5 CLOCK
PPG0
Pin
PPG1
Pin
PPG2
Pin
TIN0
Pin
TO0
Pin
SCK0,SIN0
Pin
SOT0
Pin
SCK1,SIN1
Pin
SOT1
Pin
TIN1
Pin
TO1
Pin
DTTI0
Pin
RTO0 RTO
5
to
Pin
FRCK
Pin
IN0 IN3
to
Pin
DTTI1
Pin
OPT0 OPT
5
to
Pin
PWI0, PWI1
Pin
PWO0, PWO1
Pin
79