Table of Contents
Advertisement
■ Counter Operating State
The counter status is determined by the CNTE bit of the timer control status register (TMCSRL0/
TMCSRL1) and the internal WAIT signal. Possible settings include the stop status (STOP state), trigger
wait state (WAIT state), and running state (RUN state).
Figure 12.6-3 shows the transitions of the counter state.
Reset
CNTE = 0
WAIT
TIN: Only trigger input enabled
TO: Output initial value
Counter: The counter value is
retained when the counter
stops. Immediately after a
reset, it is undefined and
remains so until a value is
loaded.
External trigger from TIN
: State transitions by hardware
: State transitions by register access
WAIT:
Wait signal (internal signal)
TRG:
Software trigger bit of timer control status register (TMCSRL0/TMCSRL1)
CNTE:
Count enable bit of timer control status register (TMCSRL0/TMCSRL1)
Underflow interrupt flag bit of timer control status register (TMCSRL0/TMCSRL1)
UF:
RELD:
Reload selection bit of timer control status register (TMCSRL0/TMCSRL1)
Figure 12.6-3 Counter State Transition
STOP
TIN: Input disabled
TO: General-purpose port
Counter:
The counter value is
retained when the counter
stops. Immediately after a
reset it is undefined.
CNTE = 1
TRG = 0
CNTE = 1, WAIT = 1
UF = 1 &
RELD = 0
(Single-shot mode)
TRG = 1
(Software trigger)
LOAD
Load contents of the reload
register into the counter.
CHAPTER 12 16-BIT RELOAD TIMER
CNTE = 0, WAIT = 1
CNTE = 1
TRG = 1
RUN
TIN: Functions as TIN
TO: Functions as TO
Counter: Running
UF = 1 &
RELD = 1
(Reload mode)
CNTE = 1, WAIT = 0
CNTE = 0
CNTE = 1, WAIT = 0
TRG = 1
(Software trigger)
Load complete
245
Advertisement
Table of Contents
