Fujitsu MB90460 Series Hardware Manual page 365

CHAPTER 14 MULTI-FUNCTIONAL TIMER
■ Making Non-overlap Signals by using PPG in Inverted Polarity
(DTCR0/DTCR1/DTCR2:TMD2 to TMD0=111
When selecting non-overlap signal for an active level "1" (inverted polarity) in DTCR0/DTCR1/
DTCR2:DMOD, a delay corresponding to the non-overlap time set in the TMRR0/TMRR1/TMRR2
register (16-bit timer register) is applied. The delay is applied at a rising edge of PPG timer 0 pulse signal
or its inverted signal. If PPG timer 0 pulse width is smaller than the set non-overlap time, the 16-bit timer
will start down-counting from TMMR0/TMMR1/TMMR2 value at the next edge of PPG0 pulse.
Figure 14.6-28 Non-overlap Signal Generation by PPG0 in Inverted Polarity
Setting up registers:
• TCDT
• TCCS
• CPCLR
• OCCP0 to OCCP5
• OCS0 to OCS5
• DTCR0 to DTCR2
• TMRR0 to TMRR2
• SIGCR
Note: "X" must be set according to the operation.
16-bit timer 0
Count
value
PPG0
RTO0 (U)
RTO1 (X)
Pin name
RTO0 (U)
RTO2 (V)
RTO4 (W)
RTO1 (X)
RTO3 (Y)
RTO5 (Z)
346
: 0000
H
: XXXXXXXXXX0X0XXX
: XXXX (Cycle setting)
H
:XXXX (Compare value)
H
: -XX1XXXXXXXXXX11
: 1XXXX111
B
: XXXX (Non-overlap timing setting)
H
: XXXXXXXX
B
1 machine cycle
Inverted signal with delay is applied at PPG0 rising edge
Inverted signal with delay is applied at PPG0 rising edge
Inverted signal with delay is applied at PPG0 rising edge
Signal with delay is applied at PPG0 falling edge
Signal with delay is applied at PPG0 falling edge
Signal with delay is applied at PPG0 falling edge
)
B
• PCSR
• PDUT
B
• PCNT
B
(DTTI0 input and 16-bit timer count clock setting)
Output signal
: XXXX
H
: XXXX
H
: XXXX
H
TMRR0 set value
1.5 machine cycle