Timer Control Status Register (Tmcsr) - Fujitsu F2MC-16LX Hardware Manual

16.2.1 Timer Control Status Register (TMCSR)

This section describes the configuration and functions of the timer control status
register (TMCSR).
I Timer control status register (TMCSR)
The timer control status register (TMCSR) is used to control the operation mode and interrupts
of the16-bit reload timer. If CNTE = 0, bits other than UF/CNTE/TRG are modified.
The figure below shows the bit configuration of the timer control status register (TMCSR).
0000CB 15
H
-
(-)
(-)
7
0000CA MOD0 OUTE OUTL RELD INTE
H
(R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing
(0)
The functions of the bits in the timer control status register (TMCSR) are described below.
[Bits 11, 10] CSL1, CLS0 (Clock selection)
These bits are used to select the clock source using the count clock selection bit.
CSL1
0
0
1
1
[Bits 9, 8, 7] MOD2, MOD1, MOD0
These bits are used to set the operation mode and functions of the input/output pin functions.
With MOD2 = 0, the input pin operates as a trigger. If an active edge is input to the input pin
while count operation is in progress, the data from the reload register is loaded into the
counter. With MOD2 = 1, the timer operates in gate counter mode and the input pin operates
as a gate input. In this mode, the counter only counts when the active level is applied to the
input pin.
By combination of the MOD2 to MOD0 bits, the internal clock mode and event counter mode
are selected from the modes listed in Table 16.2-1 "Internal clock mode (CLS1/0 = "00", "01",
or "10")" and Table Table 16.2-2 "Event counter mode (CLS1, 0 = "11")".
14 13 12 11
- - - CSL1 CSL0 MOD2 MOD1 Timer control status register (upper bits)
(-) (-) (-) (R/W) (R/W) (R/W) (R/W) Reading/writing
(-) (-) (-) (0)
6 5 4 3
(0) (0) (0) (0)
CSL0
φ/2 1 (0.125 µs) (initial value)
0
φ/2 3 (0.5 µs)
1
φ/2 5 (2.0 µs)
0
1 Event count mode
CHAPTER 16 16-BIT RELOAD TIMER
10 9 8 TMCSR
(0) (0) (0) Initial value
2 1 0 TMCSR
UF CNTE TRG Timer control status register(lower bits)
(0) (0) (0) Initial value
Clock source (machine clock: φ φ φ φ = 16 MHz)
315