Fujitsu MB90460 Series Hardware Manual page 15

16.6.4 Pulse Width Measurement Mode Operation .............................................................................. 456
16.7 Usage Notes on the PWC Timer .................................................................................................... 461
16.8 Sample Programs for the PWC Timer ............................................................................................ 464
CHAPTER 17 UART ........................................................................................................ 467
17.1 Overview of UART .......................................................................................................................... 468
17.2 Block Diagram of UART .................................................................................................................. 470
17.3 UART Pins ...................................................................................................................................... 473
17.4 UART Registers .............................................................................................................................. 475
17.4.1 Serial Control Register (SCR0/SCR1) ....................................................................................... 476
17.4.2 Serial Mode Register (SMR0/SMR1) ....................................................................................... 478
17.4.3 Serial Status Register (SSR0/SSR1) ........................................................................................ 480
17.4.4 Input Data Register (SIDR0/SIDR1) and Output Data Register (SOR0/SOR1) ........................ 482
17.4.5 Communication Prescaler Control Register (CDCR) ................................................................. 484
17.5 UART Interrupts .............................................................................................................................. 486
17.5.1 Reception Interrupt Generation and Flag Set Timing ................................................................ 488
17.5.2 Transmission Interrupt Generation and Flag Set Timing ........................................................... 489
17.6 UART Baud Rates .......................................................................................................................... 490
17.6.1 Baud Rates Determined Using the Dedicated Baud Rate Generator ........................................ 492
17.6.2 Baud Rates Determined Using the Internal Timer (16-bit Reload Timer 0) ............................... 495
17.6.3 Baud Rates Determined Using the External Clock .................................................................... 497
17.7 Operation of UART ......................................................................................................................... 498
17.7.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) ................................................. 500
17.7.2 Operation in Synchronous Mode (Operation Mode 2) ............................................................... 502
17.7.3 Bidirectional Communication Function (Normal Mode) ............................................................. 504
17.7.4 Master-slave Communication Function (Multiprocessor Mode) ................................................. 506
17.8 Usage Notes on UART ................................................................................................................... 509
17.9 Sample Program for UART ............................................................................................................. 510
CHAPTER 18 DTP/EXTERNAL INTERRUPT CIRCUIT ................................................. 513
18.1 Overview of the DTP/External Interrupt Circuit ............................................................................... 514
18.2 Block Diagram of the DTP/External Interrupt Circuit ...................................................................... 516
18.3 DTP/External Interrupt Circuit Pins ................................................................................................. 518
18.4 DTP/External Interrupt Circuit Registers ......................................................................................... 520
18.4.1 DTP/interrupt Cause Register (EIRR) ....................................................................................... 521
18.4.2 DTP/interrupt Enable Register (ENIR) ....................................................................................... 522
18.4.3 Request Level Setting Register (ELVR) .................................................................................. 524
18.5 Operation of the DTP/External Interrupt Circuit .............................................................................. 525
18.5.1 External Interrupt Function ........................................................................................................ 528
18.5.2 DTP Function ............................................................................................................................. 529
18.6 Usage Notes on the DTP/External Interrupt Circuit ........................................................................ 530
18.7 Sample Programs for the DTP/External Interrupt Circuit ................................................................ 532
CHAPTER 19 DELAYED INTERRUPT GENERATOR MODULE ................................... 535
19.1 Overview of the Delayed Interrupt Generator Module .................................................................... 536
19.2 Delayed Interrupt Generator Module Register ................................................................................ 537
19.3 Operation of the Delayed Interrupt Generator Module ................................................................... 538
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