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CHAPTER 4 RESET
■ Correspondence between Reset Cause Bits and Reset Causes
Figure 4.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (WDTC).
Table 4.5-1 maps the correspondence between the reset cause bits and reset causes.
Figure 4.5-2 Configuration of Reset Cause Bits (Watchdog Timer Control Register)
Watchdog timer control register
Address : 0000A8
Table 4.5-1 Correspondence between Reset Cause Bits and Reset Causes
Power-on reset
Watchdog timer overflow
External reset request via RSTX pin
Software reset request
* : Previous state retained
X: Undefined
■ Notes about Reset Cause Bits
●
Multiple reset causes generated at the same time
When multiple reset causes are generated at the same time, the corresponding reset cause bits of the
watchdog timer control register (WDTC) are set to "1".
If, for example, an external reset request via the RSTX pin and the watchdog timer overflow occur at the
same time, both the ERST bit and the WRST bit are set to "1".
●
Power-on reset
For a power-on reset, the PONR bit is set to "1", but all other reset cause bits are undefined.
Consequently, program the software so that it will ignore all reset cause bits except the PONR bit if it is
"1".
●
Clearing the reset cause bits
The reset cause bits are cleared only when the watchdog timer control register (WDTC) is read. Any bit
that corresponds to a reset cause that has already been generated once is not cleared even though another
reset is generated (its setting of "1" is retained).
74
bit
7
6
H
PONR
Read/write ⇒
(R)
(-)
(X)
(-)
Default value⇒
Reset cause
5
4
3
-
WRSTERST SRST WTE WT1 WT0
(R)
(R)
(R)
(W)
(X)
(X)
(X)
(1)
PONR
1
*
*
*
2
1
0
WDTC
(W)
(W)
(1)
(1)
WRST
ERST
X
X
1
*
*
1
*
*
SRST
X
*
*
1
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