Pwc Timer Registers - Fujitsu MB90460 Series Hardware Manual

CHAPTER 16 PWC Timer
16.4

PWC Timer Registers

Following are the PWC timer registers.
■ PWC Timer Registers
PWC control status register (Upper)
Address: ch.0 000009
ch.1 000029
Read/write
Initial value
PWC control status register (Lower)
Address: ch.0 000008
ch.1 000028
Read/write
Initial value
PWC data buffer register (Upper)
Address: ch.0 00000B
ch.1 00002B
Read/write
Initial value
PWC data buffer register (Lower)
Address: ch.0 00000A
ch.1 00002A
Read/write
Initial value
Division rate control register
Address: ch.0 00000C
ch.1 00002C
Read/write
Initial value
438
Figure 16.4-1 PWC Timer Registers
15 14 13
bit
H
H
STRT STOP EDIR
R/W R/W R
0 0 0
7 6 5
bit
H
H CKS1 CKS0
Reserved
R/W R/W R/W
0 0 0
bit
15 14 13
H
PW15 PW14 PW13
H
R/W R/W R/W
X X X
bit
7 6 5
H
PW07 PW06 PW05
H
R/W R/W R/W
X X X
bit
7 6 5
H
—
— —
H
12 11 10
EDIE OVIR OVIE ERR
R/W R/W R/W
0 0 0
4 3 2
S/C MOD2 MOD1 MOD0
Reserved
R/W R/W R/W
0 0 0
12 11 10
PW12 PW11 PW10
R/W R/W R/W
X X X
4 3 2
PW04 PW03 PW02
R/W R/W R/W
X X X
4 3 2
— — —
9 8
POUT
PWCSH0,
PWCSH1
R R/W
0 0
1 0
PWCSL0,
PWCSL1
R/W R/W
0 0
9 8
PW09 PW08
PWC0,PWC1
R/W R/W
X X
1 0
PW01 PW00
PWC0,PWC1
R/W R/W
X X
1 0
DIV0,DIV1
DIV1 DIV0
R/W R/W
0 0