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Operation in single-shot mode
When an underflow of the counter value (from 0000
state. If the underflow interrupt flag (TMCSRL0/TMCSRL1:UF) bit is set to "1" and the underflow
interrupt enable (TMCSRL0/TMCSRL1:INTE) bit is "1", an interrupt request is generated.
The timer can also output from the TO0/TO1 pin a rectangular waveform indicating that counting is in
progress.
Figure 12.6-11 shows counting in single-shot mode.
Figure 12.6-11 Counter Operation in Single-shot Mode (Event Count Mode)
Data load signal
CNTE bit
T: Machine cycle
* It takes 1T time from trigger input to loading of the reload data.
Note:
Specify 4/φ or more for the H and L widths of the clock input to the TIN0/TIN1 pin.
TIN pin
Reload data
Counter
UF bit
TRG bit
TO pin
CHAPTER 12 16-BIT RELOAD TIMER
to FFFF
) occurs, the counter stops in the FFFF
H
H
Reload data
Wait for trigger input
H
251
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