Fujitsu MB90460 Series Hardware Manual page 502

When data to be transmitted is written to this register in transmission enable state, it is transferred to the
transmission shift register, then converted to serial data, and transmitted from the serial data output terminal
(SOT0/SOT1 pin). When the data length is 7 bits, the uppermost bit (D7) contains invalid data.
When transmission data is written to this register, the transmission data empty flag bit (SS0/SS1: TDRE) is
cleared to "0". When transfer to the transmission shift register is complete, the bit is set to "1". When the
TDRE bit is "1", the next piece of transmission data can be written. If output transmission interrupt
requests have been enabled, a transmission interrupt is generated. Write the next piece of transmission data
when a transmission interrupt is generated or the TDRE bit is "1".
Note:
SODR0/SODR1 is a write-only register and SIDR0/SIDR1 is a read-only register. These registers are
located in the same address, so the read value is different from the write value. Therefore,
instructions that perform a read-modify-write (RMW) operation, such as the INC/DEC instruction,
cannot be used.
CHAPTER 17 UART
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