Fujitsu MB90460 Series Hardware Manual page 130

■ Release of Stop Mode
To use an external interrupt for releasing stop mode, use an input that has been set as an interrupt input
cause before the system enters stop mode. As an input cause, H level, L level, rising edge or falling edge
can be selected.
■ Release of Time-base Timer Mode
When time-base timer mode is released, the microcontroller is placed in the PLL clock oscillation
stabilization wait state. If the PLL clock is not used, change the MCS bit of the clock selection register
(CKSCR) to "1" with the instruction that is to be executed immediately after a reset or on return from an
interrupt.
If an external interrupt is used to release time-base timer mode, the input cause can be selected as H level,
L level, rising edge or falling edge.
■ Oscillation Stabilization Wait Interval
●
Source clock oscillation stabilization wait interval
Because the oscillator for source oscillation is halted in stop mode, an oscillation stabilization wait interval
is required. A time period selected by the WS1 and WS0 bits of CKSCR is used as the oscillation
stabilization wait interval.
●
PLL clock oscillation stabilization wait interval
The CPU may be working with the main clock and the PLL clock may be stopped. If the microcontroller
will enter a mode in which the CPU and peripheral functions work with the PLL clock, the PLL clock
initially enters the oscillation stabilization wait state. In this state, the CPU still operates using the main
clock.
The PLL clock oscillation stabilization wait interval is fixed at 2
frequency).
However, this interval may range from 2
base timer, if the time-base timer is not cleared before the PLL clock oscillation stabilization wait state is
entered. (For example, return to the PLL run state from time-base timer mode occurs because of an
external reset.)
■ Switching the Clock Mode
When the clock mode is switched, do not switch to low power consumption mode and other clock mode
before this switching is completed. Confirm the completion of clock mode switching by referring to the
MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched to another clock
mode or low-power-consumption mode before completion of switching, the mode may not be switched.
CHAPTER 6 LOW POWER CONSUMPTION MODE
14 14
/HCLK to 2 x 2 /HCLK depending on the status of the time-
14
/HCLK (HCLK: oscillation clock
111