ST STM32G0 1 Series Reference Manual page 1273

RM0444 Universal serial bus full-speed host/device interface (USB)
required to STALL the transaction in the case of errors. To do so, at all data stages before
the last, the unused direction should be set to STALL, so that, if the host reverses the
transfer direction too soon, it gets a STALL as a status stage.
While enabling the last data stage, the opposite direction should be set to NAK, so that, if
the host reverses the transfer direction (to perform the status stage) immediately, it is kept
waiting for the completion of the control operation. If the control operation completes
successfully, the software changes NAK to VALID, otherwise to STALL. At the same time, if
the status stage is an OUT, the STATUS_OUT (EPKIND in the USB_CHEPnR register) bit
should be set, so that an error is generated if a status transaction is performed with non-
zero data. When the status transaction is serviced, the application clears the STATUS_OUT
bit and sets STATRX to VALID (to accept a new command) and STATTX to NAK (to delay a
possible status stage immediately following the next setup).
Since the USB specification states that a SETUP packet cannot be answered with a
handshake different from ACK, eventually aborting a previously issued command to start
the new one, the USB logic does not permit a control endpoint to answer with a NAK or
STALL packet to a SETUP token received from the host.
When the STATRX bits are set to 01 (STALL) or 10 (NAK) and a SETUP token is received,
the USB accepts the data, performing the required data transfers and sends back an ACK
handshake. If that endpoint has a previously issued VTRX request not yet acknowledged by
the application (for example VTRX bit is still set from a previously completed reception), the
USB discards the SETUP transaction and does not answer with any handshake packet
regardless of its state, simulating a reception error and forcing the host to send the SETUP
token again. This is done to avoid losing the notification of a SETUP transaction addressed
to the same endpoint immediately following the transaction, which triggered the VTRX
interrupt.
Control transfers in Host mode
Control transfers are made of a SETUP transaction, followed by zero or more data stages,
all of the same direction, followed by a status stage (a zero-byte transfer in the opposite
direction). SETUP transactions are handled by control endpoints only. A control endpoint
must set the SETUP bit in the USB_CHEPnR register. The values of DTOGTX and
DTOGRX bits of the addressed endpoint registers are set to 0. Depending on whether it is a
control write or control read then STATTX or STATRX are set to 11 (ACTIVE) in order to
trigger the control transfer via the host frame scheduler.
On receiving a CTR interrupt the channel (device address and endpoint) can be determined
by examining IDN and DIR bits. Devices are expected to NAK every control unless the
packet is corrupted in which case they do not acknowledge. The situation is reflected in the
value of STATTX.
In the case of an error condition the ERR bit gets set. One possible case is where a CRC
error is seen at the device, in this case no ACK is returned to the host. The host sees no
ACK and after an appropriate delay this generates a timeout error with ERR_TX set (which
can generate an interrupt).
RM0444 Rev 5 1273/1390
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