ST STM32G0 1 Series Reference Manual page 1268

Universal serial bus full-speed host/device interface (USB)
When a RST_DCON interrupt is received, the application software is responsible to enable
again the default endpoint of USB function 0 within 10 ms from the end of the reset
sequence which triggered the interrupt.
USB bus reset in Host mode
In Host mode a bus reset is activated by setting the USBRST bit of the USB_CNTR register.
It should subsequently be cleared by software once the minimum active reset time from the
standard has been respected.
Structure and usage of packet buffers
Each bidirectional endpoint may receive or transmit data over the bus. The received data is
stored in a dedicated memory buffer reserved for that endpoint, while another memory
buffer contains the data to be transmitted by the endpoint. Access to this memory is
performed by the packet buffer interface block, which delivers a memory access request
and waits for its acknowledgment. Since the packet buffer memory has also to be accessed
by the microcontroller, an arbitration logic takes care of the access conflicts, using half
APB1 cycle for microcontroller access and the remaining half for the USB peripheral
access. In this way, both agents can operate as if the packet memory would be a dual-port
SRAM, without being aware of any conflict even when the microcontroller is performing
back-to-back accesses. The USB peripheral logic uses a dedicated clock. The frequency of
this dedicated clock is fixed by the requirements of the USB standard at 48 MHz, and this
can be different from the clock used for the interface to the APB1 bus. Different clock
configurations are possible where the APB1 clock frequency can be higher or lower than the
USB peripheral one.
Note: Due to USB data rate and packet memory interface requirements, the APB1 clock must
have a minimum frequency of 12 MHz to avoid data overrun/underrun problems.
Each endpoint is associated with two packet buffers (usually one for transmission and the
other one for reception). Buffers can be placed anywhere inside the packet memory
because their location and size is specified in a buffer description table, which is also
located in the packet memory. Each table entry is associated to an endpoint register and it is
composed of two 32-bit words so that table start address must always be aligned to an 8-
byte boundary. Buffer descriptor table entries are described in
descriptor
double-buffered bulk, only one packet buffer is required (the one related to the supported
transfer direction). Other table locations related to unsupported transfer directions or
unused endpoints, are available to the user. Isochronous and double-buffered bulk
endpoints have special handling of packet buffers (Refer to
transfers in Device mode
Device mode
packet buffer areas is depicted in
For Host mode different sections explain the buffer usage model, notably
Isochronous transfers in Host mode
Host mode.
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table. If an endpoint is unidirectional and it is neither an isochronous nor a
and Section 37.5.3: Double-buffered endpoints and usage in
respectively). The relationship between buffer description table entries and
Figure 402.
and Section 37.5.4: Double buffered channels: usage in
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Section 37.6.2: Buffer
Section 37.5.5: Isochronous
Section 37.5.6:
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